Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
a day ago
... EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of ... engineer will be working on cutting-edge technologies such as LPDDR5X, PCIe ...
7 days ago
... & Power Integrity Engineer to support high-speed interfaces (LPDDR5X, PCIe Gen7, UCIe ...
7 days ago
... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... will work closely with design, verification, and product engineering teams to ...
7 days ago