Description: Position: PCIe Validation Engineer Experience: 5 8 Years Location : San ... Python, Lab Tools Role Highlights: PCIe subsystem validation on SoC platformsPost ... and debuggingFirmware integration and PCIe trainingPerformance and reliability testing ...
14 days ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
15 days ago
Description: Job Title: GPU Design Verification Engineer Location: San Jose, CA (Onsite) ... are seeking a highly skilled Design Verification Engineer to join our team at ... be on developing and executing verification plans, creating testbenches, and debugging ...
21 days ago
... are seeking a highly skilled Design Verification Engineer to join our team.The ... be on developing and executing verification plans, creating testbenches, and debugging ... . Responsibilities Develop and execute comprehensive verification plans for GPU
22 days ago
Description: Skill Need: PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
15 days ago
Description: ResponsibilitiesOwn verification of entire FPGA design ... and interact with design engineers to identify verification scenariosCreate test plans, constrained ... -random verification environments, test cases, regressions, and ...
17 days ago
Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
a day ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
6 days ago
... IP is hiring for a Verification Engineer to join their high-performance ... team! Responsibilities include: - Developing verification environments using System Verilog and ... UVM - Designing verification components and behavioral models - ...
16 days ago
$85
$90
an hour
Description: SerDes Validation Engineer San Jose, CA (100% Onsite) 6 + ... Have Skills: SerDes HW validation, PCIe & 800G Ethernet, Python, firmware Role ... + 5 yrs experience Strong SerDes validation (PCIe/Ethernet) Python scripting & automation Firmware ...
13 days ago
Description: Job Title: Software Engineer - PCIe Driver Development Location: San Jose, ...
14 days ago
... EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of ... engineer will be working on cutting-edge technologies such as LPDDR5X, PCIe ...
7 days ago
... looking for Senior Hardware Engineer for our client in ... CA Job Title: Senior Hardware Engineer Job Location: San Jose, ... - $88.86hrThe Senior Hardware Engineer will be responsible for validating ... interfaces with a focus on PCIe and 800G Ethernet technologies. ...
13 days ago
Description: Position: Hardware Design Engineer (Architect) Location: San Jose, USA ... , oscilloscopes, multi-meters, signal generators, PCIe Gen5/6, LPDDR5/6 5 - 8 years of experience ...
2 days ago
... & Power Integrity Engineer to support high-speed interfaces (LPDDR5X, PCIe Gen7, UCIe ...
7 days ago
... : Position: SOC Post Silicon Validation Engineer Exp: 10+ years Location: San ... of SoC peripherals, including LPDDRx, PCIe, I2C, and qSPI.Manage and ...
8 days ago
... , and resource utilization (CPU, Memory, PCIe). Reliability Validation: Conduct Mean Time ...
13 days ago
... Description: Position: FPGA Verification Contractor Location: San Jose ... Description & Responsibilities Own verification of theentire FPGA designused ... engineersto identify verification scenariosCreatetest plans,constrained-random verification environments,test ...
16 days ago
... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... will work closely with design, verification, and product engineering teams to ...
7 days ago
... Senior ASIC/RTL Design Engineer for our client in ... : Senior ASIC/RTL Design Engineer Job Location: San Jose, ... 78.78hrThe ASIC/RTL Design Engineer Senior is responsible for designing ... close collaboration with architecture, verification, and physical design teams ...
29 days ago
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