... (Hybrid) Project descriptionThe Principal Design Verification Engineer, within the NPU Hardware & ... a broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
... Project Description: The Principal Design Verification Engineer, within the NPU Hardware & ... broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
8 days ago
... looking for a FPGA Verification Engineer. Role:: FPGA Verification Engineer Location: Mountain View, ... System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys ...
15 days ago
Description: Position: FPGA Verification Engineer Location: Mountain View, CA (On- ... in System Verilog and UVM verification methodology Skill 3 Experience in FPGA ... verification Good To have Skills Skill 1 ...
10 days ago
Description: FPGA Verification EngineerMountain View, CA (On-Site) ... Verilog and UVM verification methodologySkill 3 Experience in FPGA verification Good To have ... experience in FPGA design or verification. Familiarity wit
13 days ago
Description: Position: Principal Engineer, Design Verification (NPU) Location: Mountain View ... Project description The Principal Design Verification Engineer, within the NPU Hardware ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
Description: Title: Principal Engineer, Design Verification (NPU) Location: Mountain View, ... Project Description: The Principal Design Verification Engineer, within the NPU Hardware & ... experience in AI accelerator verification and automotive safety standards. ...
3 days ago
... Description: Project descriptionThe Principal Design Verification Engineer, within the NPU Hardware & ... broad background in design verification and complex digital system validation ... experience in AI accelerator verification and automotive safety standards. ...
7 days ago
... Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite ... in System Verilog and UVM verification methodology. Experience with industry ... -standard verification tools (e.g., QuestaSim, Synopsys VCS). ...
a month ago
... , timing closure, proficient in physical verification and other signoff checks with ... resolve issues wrt constraints validation, verification, STA, Physical design, etc.Partner ...
7 days ago