Description: Role: Signal Integrity and Power Integrity (SI/PI) Design Engineer Location: San Jose, ... Type: Contract SI/PI Design Engineer Responsibilities: Lead chip-package- ... by analyzing and optimizing signal and power integrity requirements. Define power ...
27 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ... of digital design for mixed-signal control loops and experience writing ...
27 days ago
... Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100 ... % Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip ... co-design by driving signal and power integrity requirements analysis and optimizationDefine ...
6 days ago
... an opening for Mixed-Signal Design Verification Engineer with our Client at ... of digital design for mixed signal control loops and designing Verilog ...
8 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key ... of digital design for mixed signal control loops and designing Verilog ...
27 days ago
... with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog ... simulations and work with design engineers to verify fixes. Write diagnostics ...
4 days ago
Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ... background in SOC/VLSI/Mixed Signal IC bring-up, production testing ...
27 days ago
... is looking for a FPGA Verification Engineer to work onsite in San ... . The ideal FPGA Verification Engineer will ensure the integrity and functionality of ... UVM. Responsibilities for FPGA Verification Engineer: Develop and implement object-oriented ...
26 days ago