... ) for complex chip-level ASIC designs Perform static timing analysis (STA ... with RTL, architecture, and physical design teams on clock structures and ...
5 hours ago
... : Chip-Level Timing Constraint Development Engineer Location: San Jose, CA Onsite ... a Chip-Level Timing Constraint Development Engineer, you will be responsible for ... teams, including RTL designers, physical design engineers, and verification teams, to ensure ...
8 hours ago