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Jobs and careers for senior director for rtl design in San Jose (2 jobs)

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ASIC Timing Engineer

  • Smksoft
  • San Jose
... ) for complex chip-level ASIC designs Perform static timing analysis (STA ... with RTL, architecture, and physical design teams on clock structures and design intent ...
17 hours ago

Chip-Level Timing Constraint Development Engineer

  • Smksoft
  • San Jose
... timing constraints for complex ASIC designs at the chip level. Your ... cross-functional teams, including RTL designers, physical design engineers, and verification teams ...
20 hours ago

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