Description: Job Description: Key Skills :Cisco SD-WAN (Viptela):Proven hands-on experience with Cisco SD-WAN solutions including deployment, troubleshooting, and optimization. Network Automation using Python:Strong expertise in Python scripting for ...
24 days ago
... team of engineers involved in the specification, design, development, and test of hardware ... closely with hardware design engineers, software/diagnostic engineers, and manufacturing test engineers to determine a product ...
23 days ago
... Description: Job Description: Thermal Engineer Duration: Contract Role / ... CA (Onsite) A thermal test engineer is primarily responsible for ... designing and conducting thermal tests on components or ... and ensuring that the design meets thermal requirements by ...
a day ago
... Engineer (Frontend) San Jose, CA - onsite What You'll Do * Design, develop, test ... product managers, business stakeholders, backend engineers, and users to translate requirements ... UI/UX best practices, proposing design improvements, and implementi
22 days ago
... have As an embedded software engineer, you will join a collaborative team ... software development cycle, including requirements, design, implementation, test, integration, and documentation in ...
24 days ago
Description: Role : EDVT Engineer Location: San Jose, CA (Onsite ... and field concepts to product test Ability to draw parallels betwee
27 days ago
Description: PSV PCIE Validation & Emulation Engineer Experience: 5 to 8 years Salary Range: ... Create and document PCIe validation test plans, test cases, and scripts. Perform ... . Collaborate with hardware/software design teams for successful integration and ...
10 days ago
... -up, simulation, integration, and validation. Test wireless subsystem performance against quality ... metrics. Automate test equipment to optimize test cycle efficiency. Help ...
9 hours ago
Description: Job Title: SoC Lead Engineer Location: San Jose, CA Company: ... ) and design clock/reset architectures.Collaborate with verification teams for test planning ...
16 days ago
... Title: Power & Performance (PnP) Validation Engineer Location: San Jose, CA Company ... Responsibilities: Validate ARM-based SoC designs focusing on power, performance, and ... lab tools.Develop testbenches and test cases for RTL/firmware verification ...
10 days ago
... , C++, MATLAB and LabVIEW. Lab and test experience (hands-on) is a must ...
2 days ago
... , C++, MATLAB and LabVIEW. Lab and test experience (hands-on) is a must ...
9 days ago
... , C++, MATLAB and LabVIEW. Lab and test experience (hands-on) is a must ...
23 days ago
... biotech organization is seeking a Research Engineer to support the development of ... , and laser cutting Assemble and test mesofluidic/microfluidic and electro-mechanical ...
28 days ago
Description: Physical Design Engineer Long term Contract First preference : ... executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... in understanding and writing synthesis design constraints for hierarchical physical partitions ...
10 hours ago
Description: Position: ML/AI Engineer with robotics Duration: 12+ months ... DESCRIPTION SKILLS NEEDED : ML/AI Engineer with robotics, Gen AI Job ... . Experience of app design development architecture Have deployed, tested and optimized machine ...
a day ago
Description: Position: Physical Design Engineer Location: San Jose CA (Day-1 ... Be Doing: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
7 days ago
Description: Position: STA Engineer Location: San Jose CA (Day-1 ... Be Doing: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
9 hours ago
Description: SDC Engineer Location: San Jose CA (Day-1 ... Be Doing: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
6 days ago
... Be Doing: Being a member of design team who oversees full chip ... SDCs and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
7 days ago