Description: Job Title: System IP Design Verification Engineer Duration: 6 Months Location: ... . Job Description As a Senior Staff System IP Design Verification Contractor you will ...
20 days ago
... open-source LLMs for RTL (Register Transfer Level) design. The ideal candidate ... will work closely with RTL domain experts ... develop and optimize AI-assisted RTL integration workflows. The role involves ...
15 days ago
$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, ... : Good knowledge of System-Verilog RTL coding including state machines, adders ... , etc. Good understanding of digital design for mixed signal control loops ...
13 days ago
$50
$75
an hour
... Jose, CA that is seeking a Senior Product/UX Designer to join ... SaaS Collaboration product. Responsibilities: * The Senior Product/UX Designer will collaborate ... * Leverage user feedback to guide design decisions and ensure the p
27 days ago
Description: PEGA Senior System Architect Onsite Preference: Onsite- ... 2 complex projects with PEGADevelop and design applications using PEGA PRPC components ...
28 days ago
... Description: LLM Engineer AI-Assisted RTL Integration Location: Bay Area, ... source LLMs for RTL (Register Transfer Level) design. The ideal ... candidate will work closely with RTL domain ... and optimize AI-assisted RTL integration workflows. The ...
15 days ago
... Description: LLM Engineer AI-Assisted RTL Integration Location: Bay Area, ... source LLMs for RTL (Register Transfer Level) design. The ideal ... candidate will work closely with RTL domain ... and optimize AI-assisted RTL integration workflows. The ...
19 days ago
... : Strong knowledge of System-Verilog RTL coding, including state machines, adders ... logic. Solid understanding of digital design for mixed-signal control loops ...
12 days ago