... UVM, System Verilog, SVA Develop test plans and coverage metrics from ... write block and chip-level tests in C,SV,UVM Debug RTL ... Gate simulations and work with design engineers to verify fixes. Write diagnostics ...
29 days ago
Description: Title: Design Verification Engineer Location: San Jose, CA Duration: ... in verificationProven experience with digital design, lab skills, and debugging in ... System verilogtest cases for digital design verification.Perform FPGA designt
25 days ago