Description:
Title: Design Verification Engineer Location: San Jose, CA Duration: Long-term extending contract (5 years+) Hours: 8-5pm but flexible Interview Process: 2 rounds, can lock within a week. Must Haves: UVM and System Verilog10 years of experience in verificationProven experience with digital design, lab skills, and debugging in FPGA environments Nice to Have: Networking systems knowledge Day to Day: Develop and modify System verilogtest cases for digital design verification.Perform FPGA designt
Apr 14, 2025;
from:
dice.com