... Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100 ... % Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip ... simulation models and develop simulation methodology
5 days ago
... . Familiar with industry standard CAD methodologies from Cadence, Synopsys, and/or ...
6 days ago
... Power Integrity (SI/PI) Design Engineer Location: San Jose, CA 100 ... Type: Contract SI/PI Design Engineer Responsibilities: Lead chip-package-system ... power distribution structures, netlists, and methodologies for High-Performance Computing using ...
25 days ago