... interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics ... write block and chip-level tests in C,SV,UVM Debug RTL ... simulations and work with design engineers to verify fixes. Write diagnostics ...
15 days ago
Description: Title: Design Verification Engineer Location: San Jose, CA ... . Must Haves: UVM and System Verilog10 years of experience in ... Nice to Have: Networking systems knowledge Day to Day: ... Develop and modify System verilogtest cases for digital ...
12 days ago