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Jobs and careers for system debug lead engineer in San Jose (2 jobs)

Design verification engineer
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Design Verification Engineer

  • Mirafra Inc
  • San Jose
... mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans ... ,UVM Debug RTL and Gate simulations and work with design engineers to ...
20 days ago

Design Verification Engineer

  • Collaborate Solutions, Inc.
  • San Jose
Description: Title: Design Verification Engineer Location: San Jose, CA ... . Must Haves: UVM and System Verilog10 years of experience in ... Nice to Have: Networking systems knowledge Day to Day: ... Develop and modify System verilogtest cases for digital ...
17 days ago

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