Description: Title: Design Verification Engineer Location: San Jose, CA ... . Must Haves: UVM and System Verilog10 years of experience in ... Nice to Have: Networking systems knowledge Day to Day: ... Develop and modify System verilogtest cases for digital ...
17 days ago
... mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans ... simulations and work with design engineers to verify fixes. Write diagnostics ...
20 days ago