Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
a day ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, ... Take lead responsibility for validating PCIe and its subsystems on multiple ...
6 days ago
Description: Position: Hardware Design Engineer (Architect) Location: San Jose, USA ... , oscilloscopes, multi-meters, signal generators, PCIe Gen5/6, LPDDR5/6 5 - 8 years of experience ...
2 days ago