$85
$90
an hour
Description: SerDes Validation Engineer San Jose, CA (100% Onsite) 6 + ... -90/HR Must Have Skills: SerDes HW validation, PCIe & 800G Ethernet, Python ... or MS + 5 yrs experience Strong SerDes validation (PCIe/Ethernet) Python scripting & automation ...
23 hours ago
Description: Position: PCIe Validation Engineer Experience: 5 8 Years Location : San Jose , ... Tools Role Highlights: PCIe subsystem validation on SoC platformsPost-silicon bring ...
2 days ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, ...
3 days ago
Description: Skill Need: PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, Multimeter, Logic & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Job Description Take lead responsibility for validating PCIe and its subsystems on multiple SoC ...
3 days ago
... Senior Hardware Engineer will be responsible for validating high-speed SerDes interfaces ... Ethernet technologies.This role involves validation strategy development, production test support ... collaboration, and continuous improvement of validation methodol
a day ago
... : San Jose Summary Signal integrity engineer provides design guideline and support ... factory builds . Performs testing , simulation, validation and qualification of systems and ... as needed. The Signal integrity engineer works in cross functional teams ...
2 days ago
Description: Job Title: Senior Hardware Engineer Location: San Jose, CA, USA, ... visible role as Senior Hardware Engineer, you will Drive product from ... SI engineers to complete the designsBring up systems and execute engineering validation ...
a day ago
... QA Engineer Performance & Reliability to lead the performance characterization and reliability validation ...
2 days ago
$58
$60
an hour
... Candidates Only) FPGA/RTL Design Engineer San Jose, CA - 100% Onsite ... cycle, including architecture, design, prototyping, validation, productization, and support of IPs ...
4 days ago
... are looking for RTL Design Engineer - Intermediate for our client in ... , CA Job Title: RTL Design Engineer - Intermediate Job Location: San Jose ... development cycle through implementation, prototyping, validation, productization and support including but ...
5 days ago
... utilization (CPU, Memory, PCIe). Reliability Validation: Conduct Mean Time Between Failures ...
a day ago