Description: Job Title: Senior ASIC Design Engineer Location: San Jose, CA What ... designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA ... engage in block-level RTL design or block or top-level ...
27 days ago
Description: Job Title: Senior ASIC Design Engineer Location:San Jose ,CA Contract: ... : Technical: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to ... also do block level RTL design or block or top- ...
12 days ago