Description: Package Design Engineer in the US, please ... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
7 days ago
... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
a day ago