Description:
Package Design Engineer in the US, please share the relevant profiles ASAP. Exp: 5-8 years of experience. Location: US (San Jose) Candidate should be Onsite (Mandatory) Requirements/Skills: Possess Mentor Graphics, Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing design rule and assembly rule Possess Flip Chip Package Design Concept Good communication skill. May require vendor on-site support
Nov 18, 2025;
from:
dice.com