Description: Position: Physical Design Engineer Location: San Jose CA (Day-1 ... fullchip SDCs and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
6 days ago
Description: Physical Design Engineer Contract First preference : CA Second ... and executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... and writing synthesis design constraints for hierarchical physical partitions Experience in ...
16 days ago