Description: Position: Physical Design Engineer Location: San Jose CA (Day-1 ... Be Doing: Being a member of design team who oversees fullchip SDCs ... and works with physical design and DFT teams to close ... also do block level RTL design or block or top-level ...
19 hours ago
Description: Physical Design Engineer Contract First preference : CA Second ... executing Full-chip Hierarchical Physical Design of Mixed-signal chips. Experience ... in understanding and writing synthesis design constraints for hierarchical physical partitions ...
10 days ago