$50
$65
an hour
Description: Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA ... Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good ... . Good understanding of digital design for mixed signal control loops ...
27 days ago
Description: Title: Design Verification Engineer Location: San Jose, CA Duration: ... in verificationProven experience with digital design, lab skills, and debugging in ... System verilogtest cases for digital design verification.Perform FPGA designt
a day ago
... an opening for Mixed-Signal Design Verification Engineer with our Client at San ... , etc.Good understanding of digital design for mixed signal control loops ...
8 days ago
... implement IP/SoC verification plans, build verification test benches ... verification. Develop functional tests based on verification test plan. Drive Design Verification ... to closure based on defined verification ...
28 days ago
Description: Job Title: Design Verification (DV) EngineerLocation: Bay Area, CAJob ... are seeking a highly skilled Design Verification (DV) Engineer to join our team in ... background in Networking and SERDES verification. This role requires expertise in ...
27 days ago
... : Architect block and full-chip verification environments using HVLs and constrained ... Gate simulations and work with design engineers to verify fixes. Write diagnostics ...
4 days ago
... is looking for a FPGA Verification Engineer to work onsite in ... Verification Engineer will ensure the integrity and functionality of a digital design ... environment for FPGA design using Verilog and UVM. Responsibilities for FPGA Verification Engineer ...
26 days ago
... Companies is seeking an FPGA Verification Engineer to work onsite in San ... days per week. The FPGA Verification Engineer will ensure the robustness and ... . Responsibilities of the FPGA Verification Engineer include: Design and implement object-oriented testbench ...
3 days ago
... Companies is seeking an FPGA Verification Engineer to work onsite in San ... days per week. The FPGA Verification Engineer will ensure the robustness and ... . Responsibilities of the FPGA Verification Engineer include: Design and implement object-oriented testbench ...
11 days ago
... Companies is seeking an FPGA Verification Engineer to work onsite in San ... days per week. The FPGA Verification Engineer will ensure the robustness and ... . Responsibilities of the FPGA Verification Engineer include: Design and implement object-oriented testbench ...
18 days ago
... Companies is seeking an FPGA Verification Engineer to work onsite in San ... days per week. The FPGA Verification Engineer will ensure the robustness and ... . Responsibilities of the FPGA Verification Engineer include: Design and implement object-oriented testbench ...
22 days ago
... Companies is seeking a FPGA Verification Engineer to support an industry leader ... customers. Responsibilities of the FPGA Verification Engineer include: Developing and executing ... , and identifying and debugging design flaws Collaborating closely with FPGA ...
25 days ago
... Companies is seeking a FPGA Verification Engineer to support an industry leader ... customers. Responsibilities of the FPGA Verification Engineer include: Developing and executing ... , and identifying and debugging design flaws Collaborating closely with FPGA ...
29 days ago
... : Piper Companies is hiring a FPGA Verification Engineer for a large organization located in ... . The FPGA Verification Engineer will focus on verifying FPGA designs in routers, ensuring ... to debug failures. The FPGA Verification Engineer will need to sit on ...
25 days ago
Description: Title: Verification Engineer Location: San Jose, CA (5 days ... the testbench architecture Strong in Design Functional Verification (SV/UVM) Software (Test ...
5 days ago
Description: Role: Mixed-Signal Verification Engineer Location: San Jose, CA 100% ... logic. Solid understanding of digital design for mixed-signal control loops ...
27 days ago
... SV/UVM. Experience in complete verification cycle which includes development of ...
4 days ago
... : Job Title: Senior ASIC Design Engineer Location: San Jose, CA What ... gate SoC designs onto prototyping platforms, creating design partitions, FPGA ... in block-level RTL design or block or top ... integration. Collaborate with Software, Design, and Verification t
9 hours ago
Description: Title: Verification Test Engineer - Onsite Mandatory skills: software, firmware, ...
4 days ago
... Description: The Senior Failure Analysis Engineer will perform power supply or ... , the following. Debugging and functionality verification of AC/DC switching power ...
14 days ago