Description: Role: Post-Silicon Validation Engineer Location: San Jose, CA Hybrid ...
26 days ago
... Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100 ... % Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip ... package technologyRun pre-layout and post-layout simulation flow with a focus ...
6 days ago
... Power Integrity (SI/PI) Design Engineer Location: San Jose, CA 100 ... Type: Contract SI/PI Design Engineer Responsibilities: Lead chip-package-system ... technologies. Conduct pre-layout and post-layout simulations for high-speed ...
26 days ago
... a unique combination of pre-silicon and post-silicon expertise to provide an efficient ... turnkey solution for silicon bring-up ...
14 days ago
... a unique combination of pre-silicon and post-silicon expertise to provide an efficient ... turnkey solution for silicon bring-up ...
14 days ago