... UVM, System Verilog, SVA Develop test plans and coverage metrics from ... write block and chip-level tests in C,SV,UVM Debug RTL ... with design engineers to verify fixes. Write diagnostics for validation of FPGA ...
4 days ago
Description: Title: Design Verification Engineer Location: San Jose, CA Duration: ... +) Hours: 8-5pm but flexible Interview Process: 2 rounds, can lock within a week ...
a day ago