$90
$95
an hour
Description: Mixed Signal Model Verification Engineer San Jose, CA (Hybrid) 3 + Months $ ... -95/HR Goal: Verify SystemVerilog (logic/real number) behavioral models against ...
7 hours ago
Description: Title: Embedded Hardware Design Engineer Location: San Jose, CA (Onsite) ... , CAN, PCIe Lab Expertise: Oscilloscopes, Logic Analyzers, Signal Gene
16 hours ago