... : Cell: Job Title: Silicon Validation Engineer Location: San Jose, CA Duration ... system integration Exposure to Signal Integrity and Power Integrity. Exposure to MIPI New ...
5 days ago
... Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100 ... % Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip ... co-design by driving signal and power integrity requirements analysis and optimizationDefine ...
18 days ago
... an opening for Mixed-Signal Design Verification Engineer with our Client at ... of digital design for mixed signal control loops and designing Verilog ...
20 days ago
... with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog ... simulations and work with design engineers to verify fixes. Write diagnostics ...
16 days ago