... . Job Requirements are as below: Architect block and full-chip verification ... mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans ...
10 days ago
... a week. Must Haves: UVM and System Verilog10 years of experience in ... environments Nice to Have: Networking systems knowledge Day to Day: Develop ... and modify System verilogtest cases for digital design ...
7 days ago