... and System Verilog10 years of experience in verificationProven experience with digital design ... environments Nice to Have: Networking systems knowledge Day to Day: ... Develop and modify System verilogtest cases for digital design verification.Perform FPGA ...
5 days ago
... mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans ... Gate simulations and work with design engineers to verify fixes. Write ...
8 days ago