... an opening for Mixed-Signal Design Verification Engineer with our Client ... % Onsite Qualifications Good knowledge of System-Verilog RTL coding including state ... , etc.Good understanding of digital design for mixed signal control loops ...
12 days ago
$50
$65
an hour
... Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System ... Experience/Skills: Good knowledge of System-Verilog RTL coding including state ... , etc. Good understanding of digital design for mixed signal control loops ...
a month ago