Description: Position: PCIe Validation Engineer Experience: 5 8 Years Location : San Jose ,CA Duration : 12 months Key Skills: PCIe Gen4/5/6, CXL, RISC-V/ARM, Firmware, C/C++, Python, Lab Tools Role Highlights: PCIe subsystem validation on SoC ...
a day ago
Description: Skill Need: PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, Multimeter, Logic & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Job Description Take lead responsibility for validating PCIe and its subsystems on multiple SoC ...
2 days ago
Description: Position: PCIe Validation Engineer Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, Multimeter, Logic & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Take lead responsibility for validating PCIe and its subsystems on ...
2 days ago