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Jobs and careers for senior soc power architect from the company Coretek labs in Santa Clara (1 jobs)

Coretek labs
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Senior Manager / ASIC STA & CAD Engineering

  • Coretek Labs
  • Santa Clara
... Key Responsibilities: Developing block and SoC timing constraints, full chip STA ... flow and execution to meet SoC timing requirements including timing budgeting ... Engaging closely with block and SoC design teams to understand the ...
24 days ago

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