Description: Role Title: Senior ASIC Engineer, Static Timing Analysis Location: San Jose, CA Onsite Alternate location: Colorado office - Longmont Duration: 12+ months contract Description: Responsible for the development of complex multi-mode / multi- ...
3 days ago
Description: TOP 3 SKILLS: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have KEY RESPONSIBILITIES: Write micro- ...
6 days ago