... Subsystem Looking for a Design Verification Engineer to play a key role in ... System Verilog (SV) & UVM, with a focus on developing verification environments, executing test ...
18 hours ago
... Subsystem Looking for a Design Verification Engineer to play a key role in ... System Verilog (SV) & UVM, with a focus on developing verification environments, executing test ...
22 days ago
... a skilled AI Scale-Out Software Engineer to build and optimize our ... expertise in deep learning, distributed systems, and low-level networking. Responsibilities ... and implement efficient distributed training systems for large-scale deep le
13 days ago
... a CPU core level feature/test plan verification engineer responsible for ISA & microarchitectural ... with emphasis on core level test planning, stimulus development & regression debug ... for the Core & create comprehensive test plans. Hands-on debug for c
22 days ago