Description:
Design Verification CPU Core & Block Looking for a CPU core level feature/test plan verification engineer responsible for ISA & microarchitectural verification. This will be hybrid, based out of Austin, TX or Santa Clara, CA. Scope: Functional verification with emphasis on core level test planning, stimulus development & regression debug for simulation & emulation regressions. Understand ISA & microarchitectural specifications for the Core & create comprehensive test plans. Hands-on debug for c
Feb 18, 2025;
from:
dice.com