Description: Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead II ... highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... will work closely with design engineers to develop and execute verification pla
5 days ago
... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience in ... SystemVerilog and UVM. The engineer will own verification of complex digital IPs ... silicon. Key responsibilities - Own verification of one or more IPs ...
13 days ago
Description: Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI ... design principles, and architectures. Proficiency in SystemVerilog and UVM verification ... operating systems. Proficiency with verification tools such as QuestaSim, ...
28 days ago
Description: Job Title: FPGA Verification Engineer Location: Santa Clara, CA-Onsite ... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... FPGA design principles and architectures. Proficiency in System Verilog and UVM verification ...
4 days ago
Description: FPGA Verification Engineer Day1 Onsite (Santa Clara, CA) ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... work closely with design engineers to develop and execute verification plans, identify and ...
28 days ago
Description: FPGA Verification Engineer Santa Clara, CA Must Have ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... work closely with design engineers to develop and execute verification plans, identify and ...
28 days ago
... highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... responsible for the verification of complex FPGA designs, ensuring their functionality ... work closely with design engineers to develop and execute verification plans, identify ...
25 days ago
... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
19 days ago
... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
27 days ago
... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
27 days ago
Description: Role: FPGA Verification Engineer Location: Santa Clara, CA - Onsite ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
12 days ago
Description: Role: FPGA Verification Engineer (19921-1) Location: Santa Clara, CA - ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... be responsible for the verification of complex FPGA designs, ensuring their functionality ...
19 days ago
... looking for Performance Modeling/Verification Engineer - Intermediate for our ... Job Title: Performance Modeling/Verification Engineer - Intermediate Job Location: ... 51hr - $58hrThe Performance Modeling/Verification Engineer develops, enhances, and maintains ...
22 days ago
Description: Role: FPGA Verification Engineer (19921-1) Location: Santa Clara, CA - ... a highly motivated and skilled FPGA Verification Engineer to join our dynamic team ...
27 days ago
Description: Silicon Design Package Engineer Location Santa Clara, CA (Onsite ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
3 days ago
Description: Silicon Design Package Engineer Location Santa Clara, CA (Onsite ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
5 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA We ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
8 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA Must ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ...
15 days ago
Description: Title: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA-Onsite ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation. Develop forward ...
17 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
11 days ago