Description: Job Title: ASIC/RTL Design Verification Engineer Location: Santa Clara, CA Work ... for an adaptive, self-motivative Design Verification Engineer to join our growing team ...
15 days ago
Description: Job title : ASIC Verification Engineer Location : Santa Clara, California Local ... : 6+ months Job Description: Responsibilities: Design and implement test plans to ... and MIPI protocols.Conduct RTL design validation and debugging of adversarial ...
25 days ago
... seeking a highly experienced Modeling & Verification Engineer with strong expertise in SystemC ... key role in Performance Modeling/Verification. Responsibilities: Develop, enhance, and ... integrate models into system-level design tools, ensuring functionality and ...
28 days ago
... are looking for Performance Modeling/Verification Engineer for our client in Santa ... , CA Job Title: Performance Modeling/Verification Engineer Job Location: Santa Clara, CA ...
17 days ago
Description: Title: Performance Modeling/Verification Engineer - Onsite Description: JOB DUTIES: Develop, ... tools used for system-level designs, ensuring proper functionality and performance ...
16 days ago
... : Develop and execute comprehensive verification plans for FPGA designs. Create and maintain ... , working closely with design engineers to resolve them. Document verification results and pr
21 days ago
... a Senior SoC RTL Design Engineer to lead the SoC ... chip-top RTL design and integration, ensuring ... into a complete SoC design. The engineer will be responsible ... for RTL implementation, synthesis constraints, I/O padring design ...
29 days ago
... : Senior Software Engineer in Test (SDET) / Verification and Validation Software Engineer LOCATION: Santa ... Senior Software Engineer in Test (SDET) / Verification and Validation Software Engineer Position Summary ...
22 days ago
... : W2 - NO THIRD PARTY SDET - Verification & Validation Engineer Duration -- 9 Months Work location ... ) As a Sr Software Engineer in Test in the Software Verification & Validation team ...
15 days ago
... & No Third Party Profiles SDET - Verification & Validation Engineer Duration -- 9 Months Work location ... ) As a Sr Software Engineer in Test in the Software Verification & Validation team ...
18 days ago
... : Senior Software Engineer in Test (SDET) / Verification and Validation Software Engineer Location: Santa ... : As a Sr Software Engineer in Test in the Software Verification & Validation team ...
22 days ago
Description: Senior Software Engineer in Test (SDET) / Verification and Validation Software Engineer Duration -- 9 Months ... : As a Sr Software Engineer in Test in the Software Verification & Validation team ...
22 days ago
Description: Senior Software Engineer in Test (SDET) / Verification and Validation Software Engineer Duration -- 9 months ... ). Position Summary: As a Sr Software Engineer in Tes
18 days ago
... a highly experienced Performance Modeling Engineer with strong expertise in SystemC ... a key role in Performance Modeling/Verification. Responsibilities: Develop, enhance, and ... integrate models into system-level design tools, ensuring functionality and ...
8 days ago
... an experienced Lead Thermal Mechanical Design Engineer with specific experience in Liquid ... , California. As a member of this design team, you will have the ... cloud applications. As a Lead Thermal Engineer, you will focus on the ...
27 days ago
... experience in PCB Layout Design. Role: PCB Layout Engineer Description of Work ... Be Performed: Collaborate with product design engineers to develop high-speed, high ...
9 days ago
... Engineer - Project Management Polymer Materials Laboratory The Product Design ... Polymers Team is looking for an experienced polymer characterization engineer ... Engineering group within Product Design department. Responsibilities and activities ...
26 days ago
... : Description Working closely with product design engineers, you'll perform PCB layout ... AI), all using Cadence PCB design tools Allegro 23.1 and Capture ...
9 days ago
Description: Role: Network Security Engineer Location: Santa Clara, CA (Onsite) ... a skilled and proactive Network Security Engineer to join our team in ... , we d love to connect! Responsibilities Design, implem
12 days ago
... & More Job Description - Experienced Emulation Engineer of 8 to 10 years, responsible ... debugging complex ASIC and IP designs using the Synopsys ZeBu emulation ... , a deep understanding of the chip design lifecycle, and strong problem-so
22 days ago