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Jobs and careers for systems administrator in Santa Clara
(1 jobs)
Design verification engineer with uvm,ovm, systemverilog & python
Last month
Company
PDDN Inc
(
+1
)
Schedule
Full-day
(
+1
)
Employment
Temporary
(
+1
)
Source
dice.com
(
+1
)
Location
Santa Clara
(
+1
)
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Design Verification Engineer with UVM,OVM, SystemVerilog & Python
PDDN Inc
Santa Clara
... and Create verification environments using
System
-Verilog and Universal verification methodology ...
19 days ago
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