What
Where
0
Home Browse jobs About us Contacts
  1. Home
  2. Santa Clara
  3. Test and evaluation engineer
What
Where

Jobs and careers for test and evaluation engineer in Santa Clara (1 jobs)

Design verification engineer with uvm,ovm, systemverilog & python
Last month
Company
Schedule
Employment
Source
Location
Sort by:

Design Verification Engineer with UVM,OVM, SystemVerilog & Python

  • PDDN Inc
  • Santa Clara
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... analog mixed-signal interfaces. Develop test plans and coverage metrics from ... writing block and chip-level tests. Creat
14 days ago

Get new test and evaluation engineer jobs in Santa Clara by email

By creating a job alert, you agree to our Terms You can change your consent settings at any time by unsubscribing or as detailed in our terms.