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Jobs and careers for test manager in Santa Clara
(1 jobs)
Design verification engineer with uvm,ovm, systemverilog & python
Last month
Company
PDDN Inc
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+1
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Schedule
Full-day
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+1
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Employment
Temporary
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+1
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Source
dice.com
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+1
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Location
Santa Clara
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Design Verification Engineer with UVM,OVM, SystemVerilog & Python
PDDN Inc
Santa Clara
... analog mixed-signal interfaces. Develop
test
plans and coverage metrics from ... writing block and chip-level
tests
. Creat
14 days ago
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