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Jobs and careers for tool design in Santa Clara
(1 jobs)
Lead fpga verification engineer with uvm /verilog system-active requirement
Last week
Company
Data Capital Inc
(
+1
)
Schedule
Full-day
(
+1
)
Employment
Full-time
(
+1
)
Source
dice.com
(
+1
)
Location
Santa Clara
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+1
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement
Data Capital Inc
Santa Clara
... ) Familiarity with industry-standard verification
tools
(e.g., QuestaSim, Synopsys VCS) Experience with ...
6 days ago
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