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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

Data Capital Inc
Santa Clara Full-day Full-time

Description:

Mandate Skills: FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification experience Strong SystemVerilog programming skills Hands-on experience with UVM (Universal Verification Methodology) Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS) Experience with code and functional coverage analysis Proficient in debugging and problem-solving Scripting experience in Python or Perl Knowledge of Verilog a
Nov 28, 2025;   from: dice.com
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