Description:
Job Title: FPGA Verification Engineer Location: Santa Clara, CA-Onsite 100%, Day 1 Mon-Fri Duration: 12+ Months Mandatory Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA Skill 2 5 +Years of Exp in UVM Skill 2 5 +Years of Exp in System Verlilog Job Description: Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., Questa
Dec 5, 2025;
from:
dice.com