Description: Role: Silicon Design Package Engineer Location: Hybrid (Santa Clara, CA ... and Cadence tools (especially for Package Layout Automation - PLA). Technical ... Expertise: Multi-layer package design experience. Understanding of substrate ...
11 days ago
Description: Senior ASIC EngineerSanta Clara , CA 100% onsite ... Technologies: C++ Programming Language System Verilog ASIC Required Education: . Bachelors Degree in ...
22 days ago
... Tier 1 clients // Growing + Excellent compensation package + generous Bonus structure! This Jobot ... develops, designs, and manufactures highly engineered materials and services to Top ...
16 days ago