Description: Role: Silicon Design Package Engineer Location: Hybrid (Santa Clara, CA ... and Cadence tools (especially for Package Layout Automation - PLA). Technical ... Expertise: Multi-layer package design experience. Understanding of substrate ...
10 days ago
Description: Role: Silicon Design Package Engineer Location:Santa Clara, CA This ... and Cadence tools (especially for Package Layout Automation - PLA). Technical ... Expertise: Multi-layer package design experience. Understanding of substrate ...
28 days ago
Description: Job Title: ASIC Engineer Location: Santa Clara, CA, 95051 ... Duties and Responsibilities: Leverages advanced ASIC knowledge and experience to define ...
15 days ago
Description: Senior ASIC EngineerSanta Clara , CA 100% onsite ... Technologies: C++ Programming Language System Verilog ASIC Required Education: . Bachelors Degree in ...
21 days ago
Description: Strong understanding of FPGA, ASIC, RTL design principles and architecturesProficiency ...
20 days ago
... . Job Responsibilities Experience with 2.5D package design and development like CoWoSStrong ... expertise in using IC package layout tools like Cadence APD ... Understanding IC package design requirements for high speed ...
a day ago
... and Cadence tools (especially for Package Layout Automation - PLA).Technical Expertise ... :Multi-layer package design experience.Understanding of substrate ...
28 days ago
... Tier 1 clients // Growing + Excellent compensation package + generous Bonus structure! This Jobot ... develops, designs, and manufactures highly engineered materials and services to Top ...
15 days ago