Description:
Role: Silicon Design Package Engineer Location:Santa Clara, CA This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies Tools & Knowledge: Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA). Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing Design Rules and Assembly Rules. Familiarity with SIPI (Signal Integrity
Dec 11, 2025;
from:
dice.com