Description: Silicon Design Package Engineer Location Santa Clara, CA (Onsite) ... role is highly specialized in semiconductor packaging design, requiring strong EDA tool ... proficiency and knowledge of advanced packaging technologies Tools & Knowledge: Mentor/ ...
22 days ago
... Advanced IC Package Design Engineer (CoWoS / 2.5D Packaging)Marvell Santa Clara, CA ...
20 days ago
Description: 3-5 Years experience in system level testing of datacenter products such as GPU,CPU, debugging hardware, software, L10/L11 level testing background and good experience with python (candidate have to clear live coding test). Your duties ...
27 days ago