Description: Industrial Design Engineer 3 (W2 Role) Location: Santa Clara, ... % Are you an experienced Industrial Engineer looking to make an impact ... are seeking an Industrial Design Engineer 3 to lead continuous improvement initiatives ...
2 days ago
... are looking for a Industrial Design Engineer 3. Job Description: Job Title: Industrial ... Design Engineer 3 Job Location: Santa Clara, ... on experience Responsibilities: The Industrial Engineer 3 will lead efforts to improve ...
2 days ago
... Title: AI and BSP Engineer / Embedded Software Engineer (AI, BSP)Experience : 10 ...
7 days ago
Description: Description: We are seeking a skilled and detail-oriented Chromebook Benchmarking & Pathfinding Data Analyst to join our team. In this role, you will be responsible for performing rigorous benchmarking on Google Chromebooks. You also will be ...
3 days ago
Description: Please note that this is a 6-month contract position. Preferred Skills and Experience: - Experience working in the Medical Device/Pharma/Biotech field - Experience with computerized management systems, such as SAP, Maximo, BMRAM or CERDAAC or ...
9 days ago
Description: 6+ years of work experience responsible for designing, deploying and operating large-scale networksExperience working in a multi-vendor environment with hands-on experience with networking hardware Proven experience managing multiple projects ...
10 days ago
Description: Please note that this is a 6-month contract position. Preferred Skills and Experience: - Experience working in the Medical Device/Pharma/Biotech field - Experience with computerized management systems, such as SAP, Maximo, BMRAM or CERDAAC or ...
10 days ago
Description: FPGA & AI Model Integration: Experience with PyTorch, LLM on SoC, and AI acceleration on FPGA.RTL Development & Optimization: Proficiency in MATLAB, C, Python, GO and FEC.Parallel Computing & Memory Management: Expertise in POSIX threads, SMP ...
16 days ago
Description: Required: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements specifications Experience developing designs from scratch ...
25 days ago
Description: Looking for Lead layout design for high-performance analog cores (ADCs, DACs, PLLs, transceivers) in CMOS process nodes (5nm to 65nm). Set up LVS, DRC, and ERC environments, debug using Cadence and Mentor tools. Perform floor planning, ...
a month ago
... . Developer will work and lead engineers to customize Salesforce by creating ...
3 days ago
... conferencing. Provide support to UC engineers for Telecom projects, perform statistical ...
10 days ago
Description: Job Title: Lead Engineer - AI and FPGA Integration Expert ...
25 days ago
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