Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... -UVM IPs and SoCs with embedded CPUs and analog mixed-signal ... and writing block and chip-level tests. Creat
11 days ago
Description: Title: PCB Component Engineer (CE) Location: Santa Clara, ... per week Ideal Start Date: Mid May, beginning to review ... of his team leads and engineers Background Check Required Scope: ... The PCB Component Engineer is responsible to ensure PCBs ...
23 days ago
... MDS backbone switches Role: Storage Engineer Employment Type: Fulltime/Contract Contract ... is looking for a Senior level SAN/Storage engineer responsible for storage infrastructure ...
19 days ago
Description: Job Description Role: Storage Engineer Employment Type: Fulltime/Contract Contract 9 ... Role looking for a Senior level SAN/Storage engineer responsible for storage infrastructure ...
24 days ago
... , CA (Onsite) Job Description: Need mid-level PM who is a driver and ...
11 days ago
... dev engineers with background in firmware development, integration and validation in embedded ...
29 days ago