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Jobs and careers temporary for lead test automation engineer in Santa Clara (2 jobs)

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Design Verification Engineer with UVM,OVM, SystemVerilog & Python

  • PDDN Inc
  • Santa Clara
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... analog mixed-signal interfaces. Develop test plans and coverage metrics from ... writing block and chip-level tests. Creat
13 days ago

PCB Component Engineer

  • Oxford Global Resources
  • Santa Clara
Description: Title: PCB Component Engineer (CE) Location: Santa Clara, CA ... of several of his team leads and engineers Background Check Required Scope ... : The PCB Component Engineer is responsible to ensure PCBs ...
26 days ago

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