Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... /C/C++ Responsibilities: Architect and Create verification environments using System-Verilog and ... Universal verification methodology-UVM IPs and ...
28 days ago
Description: System Engineer_ Onsite at Santa Clara ... Ca Job Description :- Systems engineer with datacenter and server equipment ... are looking for a Systems engineer with hand-on experience with ... experience. They will also design our architecture and define our ...
22 days ago
Description: Data Engineer role with PM skills Santa ... expertise in data modeling, ETL design, and data integrationStrong understanding of ...
27 days ago
... the infrastructure through improved system design Drive a culture of intolerance to ...
14 days ago